In many data processing systems having "virtual memory", a paged memory management unit (PMMU) is used to translate a logical portion of an address provided by a processor to a memory via an address bus into a corresponding portion of a physical address. Often, associated with the PMMU is a translation cache comprising a plurality of storage locations for storing recently used translators. In response to each logical address provided by the processor, the PMMU searches the translation cache for a corresponding logical-to-physical translator. If none is found, the processor is directed to abort the access cycle and release the system bus so that the PMMU can access a set of translation tables stored in the memory to determine the proper logical-to-physical address translator to enter in the translation cache. Subsequently, when the processor restarts the aborted access cycle, the PMMU will use the new translator in the translation cache to determine the proper physical address to forward to the memory. Thereafter, whenever the processor again accesses a logical address in the same logical page, the PMMU will reuse the translator in the translation cache.
In simple virtual memory systems, there is only a single "logical address space", that of the program currently executing in the processor. Since the PMMU has access to only a single set of translation tables, the same protection and translation criteria are applied to all accesses made by that program. In some applications, however, it is desirable to provide different protections or translation criteria to certain board classes of accesses which might be made by that program.
In some virtual memory systems, a plurality of separate and distinct "address spaces" are provided and assigned as needed to particular programs. For example, in U.S. Pat. No. 4,430,705, the processor provides an "Address Space Number" together with each logical address so that the PMMU can access the particular set of translation tables appropriate for the program assigned that address space. Thus, different protections and/or translation criteria can be applied to each different address space as appropriate. On the other hand, since each program is typically assigned only a single address space, there is still no way to apply different protections or translation criteria depending upon the type of access being made by a given program.
In other virtual memory systems, not only are different address spaces assigned to the supervisor and user programs, but separate address spaces are also provided for the instructions and the data of each of these categories of programs. For example, in U.S. Pat. No. 4,084,226, the processor provides a "task name" together with each logical address to advise the PMMU which address space to use to translate that logical address. While this mechanism allows different protections and/or translation criteria to be used for those applications requiring such, for applications not requiring this level of control there is no mechanism for disabling the address space mapping. Thus, all applications automatically incur the overhead inherent in the address space control even though some do not require that control. It is therefore desirable that the PMMU be able to selectively enable the address space mapping mechanism.